OpenVera(TM) is an interoperable, open hardware verification language to accelerate innovation in the verification market, develop seamless tool integration and open distribution of verification IP. The OpenVera language was used as the basis for the advanced verification features in the IEEE Std. 1800 SystemVerilog Standard, for the benefit of the entire verification community including companies in the semiconductor, systems, IP and EDA industries along with verification services. OpenVera remains a widely adopted, evolving and well-supported hardware verification language.
OpenVera is an intuitive easy to learn language that combines the familiarity and strengths of HDLs, C++ and Java, with additional constructs targeted at functional verification making it ideal for developing testbenches, assertions and properties. OpenVera accelerates the creation of a verification environment by providing high-level constructs specifically designed for verification of complex SoCs. Designers create testbenches and assertions using OpenVera and EDA vendors create tools that are automatically interoperable.
There is broad support for OpenVera from leading companies in the community. Interested parties click through a web-based license agreement, download the OpenVera language reference manual (LRM) and proceed to use, modify or improve it--at no cost. The community will advance the standard by submitting enhancements to Synopsys, Inc., the managing entity.
OpenVera is a powerful hardware language platform for testbench creation backed by strong industry support. OpenVera fosters the rapid growth of a global market for innovative, new functional verification solutions.
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